Physical Design Engineer
Fractile is building the silicon, systems and software to break through the memory wall, the fundamental hardware constraint standing between today's AI and what comes next.
The frontier of AI is no longer a research problem. The tasks AI can complete are doubling in complexity every six to seven months and the tokens required to complete them are scaling with it. Sequential reasoning, the kind that can't be parallelised away, means the internal clock speed of inference systems is the critical constraint. What stands between where we are today and the future potential of AI isn't smarter algorithms; it's the hardware to run them fast enough to matter.
Today's chips are hitting their wall. We're building the ones that don't.
Fractile is seeking to increase the clock speed of global progress, one chip at a time.
We are seeking a Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.
Key Responsibilities:
- Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign-off.
- Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
- Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
- Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
- Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
- Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
- Work closely with RTL and architecture teams to support design feasibility, constraints, and physical-aware RTL design.
- Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 2–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
- Familiarity with EDA tools for place & route, STA, and sign-off.
- Basic understanding of CMOS technology, semiconductor physics, and process limitations.
- Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
- Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
- Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
- Interest in working with advanced AI tools and models as part of the design workflow.
- Experience or coursework in high-performance computing (HPC), AI accelerators, or networking chips is a plus
About us:
• Founded 2022, we're 100+ people across London and Bristol, in the heart of the UK's frontier AI ecosystem, and growing fast.
• We offer competitive salaries, meaningful equity, and standard company benefits.
• We believe the hardest problems get solved by the broadest range of minds. We actively encourage applications from underrepresented groups in hardware and software engineering.
• Hybrid working; 2-3 days in our London and Bristol offices.
Export controls:
Our work involves technologies subject to UK and international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.
