Jobs at Fractile

Build and maintain infrastructure and developer tooling for frontend and backend silicon teams. Integrate and support EDA tools and build systems, improve reproducible/cacheable workflows, deploy and manage cloud or on-prem compute via IaC, monitor resource usage, and optimize engineering workloads.

As a Senior System Architect, you will design system architectures for AI applications, ensuring integration and performance from concept to production by collaborating with hardware and software teams.

The Lead Physical Design Engineer will implement complex IC designs, collaborating across teams to optimize performance, power, and area while ensuring manufacturability and design integrity.

Lead and grow a 10+ engineer compiler team to build the compiler stack for a novel AI accelerator. Drive compiler architecture, IR design, lowering strategies and performance optimisation, collaborating closely with hardware, driver, runtime and ML teams to enable industry-leading LLM inference performance.

The Physical Design Engineer will implement ASIC/SoC designs, perform timing analysis, maintain design integrity, and collaborate with cross-functional teams.

Build developer-facing tooling, diagnostics, and workflows to run and optimise large language models on Fractile inference hardware. Create profiling/observability interfaces, quickstarts, docs, and examples. Advocate for external developer needs internally and collaborate with ML compiler, runtime, systems software, and silicon teams to shape APIs and abstractions.

Define and drive the architecture of compute engines, managing specifications, performance modelling, and collaborating with various teams to ensure optimal designs.

Join cross-functional teams to develop low-level software for novel SoC platforms: write/debug Linux kernel drivers (Rust), optimize instruction-level compute kernels on RISC-V/ISA, build firmware for bare-metal/RTOS/embedded Linux, extend QEMU simulators, and perform hardware-software bring-up and low-level debugging from simulation to silicon.

The Senior Logical Design Engineer will develop and implement high-performance RTL designs, collaborating with cross-functional teams, ensuring compliance with documentation and standards.

The Senior Verification Engineer will lead pre-silicon RTL verification processes, build testbenches, and improve hardware workflows in a collaborative team focused on ML/AI IC products.

As a Verification Engineer, you'll contribute to building ML/AI IC products, ensuring high standards of functional quality through collaboration on RTL verification.

Develop the ML compiler stack for AI acceleration hardware and optimize performance for large language models in a collaborative environment.

Develop Rust server software for AI inference stack, collaborate with hardware team, and conduct research for performance optimization.

Develop pre-silicon models for AI hardware, support software development, and collaborate on architecture and performance evaluation.

Develop embedded firmware and systems software for management controllers, ensuring the reliability and safety of production-critical systems. Collaborate closely with hardware teams.

As a Senior Simulation Engineer, you'll build a QEMU-based functional simulator for AI accelerator hardware and collaborate with engineers to ensure software correctness and system-level performance.

The Senior ML Runtime Engineer will integrate AI acceleration hardware with open source projects, develop high-performance Rust runtime, and collaborate on hardware-software design.

The role involves developing and implementing high-performance digital systems, ensuring clarity in RTL specifications, collaborating with design teams, and maintaining documentation and standards compliance.

Responsible for implementing complex IC physical designs, collaborating with teams to optimize performance, power, and area while ensuring design integrity and manufacturability.

The role involves optimizing ML kernels, building low-level control paths, and collaborating with various teams to enhance performance.