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Hudson River Trading

Experienced FPGA Verification Engineer

Posted 2 Days Ago
Be an Early Applicant
London, Greater London, England
Mid level
London, Greater London, England
Mid level
Experienced FPGA verification engineer at Hudson River Trading responsible for creating testbenches, writing verification plans, debugging RTL bugs, managing regression infrastructure, and developing tools. Requires strong analytical skills, experience in RTL verification, Python, Linux, and knowledge of networking protocols. Bachelor's degree in Computer or Electrical Engineering required.
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The hardware team at Hudson River Trading (HRT) creates ultra-low latency products to support our trading on global markets. High performance designs require even higher performance verification. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo.

We are looking for an experienced FPGA verification engineer who is skilled at writing testbenches and building verification environments to exercise complex hardware. FPGA verification is part of an innovative hardware team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work on critical hardware and software in an extremely fast-paced, real-time environment.

Responsibilities

  • Creating testbenches and tests for our FPGA platform, leveraging an open source-based, highly flexible environment
  • Writing detailed verification plans
  • Quickly root-cause RTL bugs
  • Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
  • Managing regression and continuous integration infrastructure
  • Developing and improving open-source and internal tools

Qualifications 

  • Excellent debug and analytical skills 
  • Strong background (4+ years) in RTL functional verification for FPGA or ASIC
  • Experience with code and functional coverage collection/analysis
  • Experience with Python
  • Comfortable in a Linux environment
  • Familiarity with Verilator and/or Cocotb preferred
  • Experience with networking protocols preferred
  • C++ experience is a plus
  • A bachelor's degree in Computer or Electrical Engineering or a related field

Culture

Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We’re a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization—from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we’re friends and colleagues – whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we’d love to get to know you.

Top Skills

Python
Verilog

Hudson River Trading London, England Office

London, United Kingdom

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